#ifndef _RV_OPCODES_H
#define _RV_OPCODES_H

// Base ISA (some of these are Z now)
#define RVOPC_BEQ_BITS         0b00000000000000000000000001100011
#define RVOPC_BEQ_MASK         0b00000000000000000111000001111111
#define RVOPC_BNE_BITS         0b00000000000000000001000001100011
#define RVOPC_BNE_MASK         0b00000000000000000111000001111111
#define RVOPC_BLT_BITS         0b00000000000000000100000001100011
#define RVOPC_BLT_MASK         0b00000000000000000111000001111111
#define RVOPC_BGE_BITS         0b00000000000000000101000001100011
#define RVOPC_BGE_MASK         0b00000000000000000111000001111111
#define RVOPC_BLTU_BITS        0b00000000000000000110000001100011
#define RVOPC_BLTU_MASK        0b00000000000000000111000001111111
#define RVOPC_BGEU_BITS        0b00000000000000000111000001100011
#define RVOPC_BGEU_MASK        0b00000000000000000111000001111111
#define RVOPC_JALR_BITS        0b00000000000000000000000001100111
#define RVOPC_JALR_MASK        0b00000000000000000111000001111111
#define RVOPC_JAL_BITS         0b00000000000000000000000001101111
#define RVOPC_JAL_MASK         0b00000000000000000000000001111111
#define RVOPC_LUI_BITS         0b00000000000000000000000000110111
#define RVOPC_LUI_MASK         0b00000000000000000000000001111111
#define RVOPC_AUIPC_BITS       0b00000000000000000000000000010111
#define RVOPC_AUIPC_MASK       0b00000000000000000000000001111111
#define RVOPC_ADDI_BITS        0b00000000000000000000000000010011
#define RVOPC_ADDI_MASK        0b00000000000000000111000001111111
#define RVOPC_SLLI_BITS        0b00000000000000000001000000010011
#define RVOPC_SLLI_MASK        0b11111110000000000111000001111111
#define RVOPC_SLTI_BITS        0b00000000000000000010000000010011
#define RVOPC_SLTI_MASK        0b00000000000000000111000001111111
#define RVOPC_SLTIU_BITS       0b00000000000000000011000000010011
#define RVOPC_SLTIU_MASK       0b00000000000000000111000001111111
#define RVOPC_XORI_BITS        0b00000000000000000100000000010011
#define RVOPC_XORI_MASK        0b00000000000000000111000001111111
#define RVOPC_SRLI_BITS        0b00000000000000000101000000010011
#define RVOPC_SRLI_MASK        0b11111110000000000111000001111111
#define RVOPC_SRAI_BITS        0b01000000000000000101000000010011
#define RVOPC_SRAI_MASK        0b11111110000000000111000001111111
#define RVOPC_ORI_BITS         0b00000000000000000110000000010011
#define RVOPC_ORI_MASK         0b00000000000000000111000001111111
#define RVOPC_ANDI_BITS        0b00000000000000000111000000010011
#define RVOPC_ANDI_MASK        0b00000000000000000111000001111111
#define RVOPC_ADD_BITS         0b00000000000000000000000000110011
#define RVOPC_ADD_MASK         0b11111110000000000111000001111111
#define RVOPC_SUB_BITS         0b01000000000000000000000000110011
#define RVOPC_SUB_MASK         0b11111110000000000111000001111111
#define RVOPC_SLL_BITS         0b00000000000000000001000000110011
#define RVOPC_SLL_MASK         0b11111110000000000111000001111111
#define RVOPC_SLT_BITS         0b00000000000000000010000000110011
#define RVOPC_SLT_MASK         0b11111110000000000111000001111111
#define RVOPC_SLTU_BITS        0b00000000000000000011000000110011
#define RVOPC_SLTU_MASK        0b11111110000000000111000001111111
#define RVOPC_XOR_BITS         0b00000000000000000100000000110011
#define RVOPC_XOR_MASK         0b11111110000000000111000001111111
#define RVOPC_SRL_BITS         0b00000000000000000101000000110011
#define RVOPC_SRL_MASK         0b11111110000000000111000001111111
#define RVOPC_SRA_BITS         0b01000000000000000101000000110011
#define RVOPC_SRA_MASK         0b11111110000000000111000001111111
#define RVOPC_OR_BITS          0b00000000000000000110000000110011
#define RVOPC_OR_MASK          0b11111110000000000111000001111111
#define RVOPC_AND_BITS         0b00000000000000000111000000110011
#define RVOPC_AND_MASK         0b11111110000000000111000001111111
#define RVOPC_LB_BITS          0b00000000000000000000000000000011
#define RVOPC_LB_MASK          0b00000000000000000111000001111111
#define RVOPC_LH_BITS          0b00000000000000000001000000000011
#define RVOPC_LH_MASK          0b00000000000000000111000001111111
#define RVOPC_LW_BITS          0b00000000000000000010000000000011
#define RVOPC_LW_MASK          0b00000000000000000111000001111111
#define RVOPC_LBU_BITS         0b00000000000000000100000000000011
#define RVOPC_LBU_MASK         0b00000000000000000111000001111111
#define RVOPC_LHU_BITS         0b00000000000000000101000000000011
#define RVOPC_LHU_MASK         0b00000000000000000111000001111111
#define RVOPC_SB_BITS          0b00000000000000000000000000100011
#define RVOPC_SB_MASK          0b00000000000000000111000001111111
#define RVOPC_SH_BITS          0b00000000000000000001000000100011
#define RVOPC_SH_MASK          0b00000000000000000111000001111111
#define RVOPC_SW_BITS          0b00000000000000000010000000100011
#define RVOPC_SW_MASK          0b00000000000000000111000001111111
#define RVOPC_FENCE_BITS       0b00000000000000000000000000001111
#define RVOPC_FENCE_MASK       0b00000000000011111111111111111111
#define RVOPC_FENCE_I_BITS     0b00000000000000000001000000001111
#define RVOPC_FENCE_I_MASK     0b11111111111111111111111111111111
#define RVOPC_ECALL_BITS       0b00000000000000000000000001110011
#define RVOPC_ECALL_MASK       0b11111111111111111111111111111111
#define RVOPC_EBREAK_BITS      0b00000000000100000000000001110011
#define RVOPC_EBREAK_MASK      0b11111111111111111111111111111111
#define RVOPC_CSRRW_BITS       0b00000000000000000001000001110011
#define RVOPC_CSRRW_MASK       0b00000000000000000111000001111111
#define RVOPC_CSRRS_BITS       0b00000000000000000010000001110011
#define RVOPC_CSRRS_MASK       0b00000000000000000111000001111111
#define RVOPC_CSRRC_BITS       0b00000000000000000011000001110011
#define RVOPC_CSRRC_MASK       0b00000000000000000111000001111111
#define RVOPC_CSRRWI_BITS      0b00000000000000000101000001110011
#define RVOPC_CSRRWI_MASK      0b00000000000000000111000001111111
#define RVOPC_CSRRSI_BITS      0b00000000000000000110000001110011
#define RVOPC_CSRRSI_MASK      0b00000000000000000111000001111111
#define RVOPC_CSRRCI_BITS      0b00000000000000000111000001110011
#define RVOPC_CSRRCI_MASK      0b00000000000000000111000001111111
#define RVOPC_MRET_BITS        0b00110000001000000000000001110011
#define RVOPC_MRET_MASK        0b11111111111111111111111111111111
#define RVOPC_SYSTEM_BITS      0b00000000000000000000000001110011
#define RVOPC_SYSTEM_MASK      0b00000000000000000000000001111111
#define RVOPC_WFI_BITS         0b00010000010100000000000001110011
#define RVOPC_WFI_MASK         0b11111111111111111111111111111111

// M extension
#define RVOPC_MUL_BITS         0b00000010000000000000000000110011
#define RVOPC_MUL_MASK         0b11111110000000000111000001111111
#define RVOPC_MULH_BITS        0b00000010000000000001000000110011
#define RVOPC_MULH_MASK        0b11111110000000000111000001111111
#define RVOPC_MULHSU_BITS      0b00000010000000000010000000110011
#define RVOPC_MULHSU_MASK      0b11111110000000000111000001111111
#define RVOPC_MULHU_BITS       0b00000010000000000011000000110011
#define RVOPC_MULHU_MASK       0b11111110000000000111000001111111
#define RVOPC_DIV_BITS         0b00000010000000000100000000110011
#define RVOPC_DIV_MASK         0b11111110000000000111000001111111
#define RVOPC_DIVU_BITS        0b00000010000000000101000000110011
#define RVOPC_DIVU_MASK        0b11111110000000000111000001111111
#define RVOPC_REM_BITS         0b00000010000000000110000000110011
#define RVOPC_REM_MASK         0b11111110000000000111000001111111
#define RVOPC_REMU_BITS        0b00000010000000000111000000110011
#define RVOPC_REMU_MASK        0b11111110000000000111000001111111

// A extension
#define RVOPC_LR_W_BITS        0b00010000000000000010000000101111
#define RVOPC_LR_W_MASK        0b11111001111100000111000001111111
#define RVOPC_SC_W_BITS        0b00011000000000000010000000101111
#define RVOPC_SC_W_MASK        0b11111000000000000111000001111111
#define RVOPC_AMOSWAP_W_BITS   0b00001000000000000010000000101111
#define RVOPC_AMOSWAP_W_MASK   0b11111000000000000111000001111111
#define RVOPC_AMOADD_W_BITS    0b00000000000000000010000000101111
#define RVOPC_AMOADD_W_MASK    0b11111000000000000111000001111111
#define RVOPC_AMOXOR_W_BITS    0b00100000000000000010000000101111
#define RVOPC_AMOXOR_W_MASK    0b11111000000000000111000001111111
#define RVOPC_AMOAND_W_BITS    0b01100000000000000010000000101111
#define RVOPC_AMOAND_W_MASK    0b11111000000000000111000001111111
#define RVOPC_AMOOR_W_BITS     0b01000000000000000010000000101111
#define RVOPC_AMOOR_W_MASK     0b11111000000000000111000001111111
#define RVOPC_AMOMIN_W_BITS    0b10000000000000000010000000101111
#define RVOPC_AMOMIN_W_MASK    0b11111000000000000111000001111111
#define RVOPC_AMOMAX_W_BITS    0b10100000000000000010000000101111
#define RVOPC_AMOMAX_W_MASK    0b11111000000000000111000001111111
#define RVOPC_AMOMINU_W_BITS   0b11000000000000000010000000101111
#define RVOPC_AMOMINU_W_MASK   0b11111000000000000111000001111111
#define RVOPC_AMOMAXU_W_BITS   0b11100000000000000010000000101111
#define RVOPC_AMOMAXU_W_MASK   0b11111000000000000111000001111111

// Zba (address generation)
#define RVOPC_SH1ADD_BITS      0b00100000000000000010000000110011
#define RVOPC_SH1ADD_MASK      0b11111110000000000111000001111111
#define RVOPC_SH2ADD_BITS      0b00100000000000000100000000110011
#define RVOPC_SH2ADD_MASK      0b11111110000000000111000001111111
#define RVOPC_SH3ADD_BITS      0b00100000000000000110000000110011
#define RVOPC_SH3ADD_MASK      0b11111110000000000111000001111111

// Zbb (basic bit manipulation)
#define RVOPC_ANDN_BITS        0b01000000000000000111000000110011
#define RVOPC_ANDN_MASK        0b11111110000000000111000001111111
#define RVOPC_CLZ_BITS         0b01100000000000000001000000010011
#define RVOPC_CLZ_MASK         0b11111111111100000111000001111111
#define RVOPC_CPOP_BITS        0b01100000001000000001000000010011
#define RVOPC_CPOP_MASK        0b11111111111100000111000001111111
#define RVOPC_CTZ_BITS         0b01100000000100000001000000010011
#define RVOPC_CTZ_MASK         0b11111111111100000111000001111111
#define RVOPC_MAX_BITS         0b00001010000000000110000000110011
#define RVOPC_MAX_MASK         0b11111110000000000111000001111111
#define RVOPC_MAXU_BITS        0b00001010000000000111000000110011
#define RVOPC_MAXU_MASK        0b11111110000000000111000001111111
#define RVOPC_MIN_BITS         0b00001010000000000100000000110011
#define RVOPC_MIN_MASK         0b11111110000000000111000001111111
#define RVOPC_MINU_BITS        0b00001010000000000101000000110011
#define RVOPC_MINU_MASK        0b11111110000000000111000001111111
#define RVOPC_ORC_B_BITS       0b00101000011100000101000000010011
#define RVOPC_ORC_B_MASK       0b11111111111100000111000001111111
#define RVOPC_ORN_BITS         0b01000000000000000110000000110011
#define RVOPC_ORN_MASK         0b11111110000000000111000001111111
#define RVOPC_REV8_BITS        0b01101001100000000101000000010011
#define RVOPC_REV8_MASK        0b11111111111100000111000001111111
#define RVOPC_ROL_BITS         0b01100000000000000001000000110011
#define RVOPC_ROL_MASK         0b11111110000000000111000001111111
#define RVOPC_ROR_BITS         0b01100000000000000101000000110011
#define RVOPC_ROR_MASK         0b11111110000000000111000001111111
#define RVOPC_RORI_BITS        0b01100000000000000101000000010011
#define RVOPC_RORI_MASK        0b11111110000000000111000001111111
#define RVOPC_SEXT_B_BITS      0b01100000010000000001000000010011
#define RVOPC_SEXT_B_MASK      0b11111111111100000111000001111111
#define RVOPC_SEXT_H_BITS      0b01100000010100000001000000010011
#define RVOPC_SEXT_H_MASK      0b11111111111100000111000001111111
#define RVOPC_XNOR_BITS        0b01000000000000000100000000110011
#define RVOPC_XNOR_MASK        0b11111110000000000111000001111111
#define RVOPC_ZEXT_H_BITS      0b00001000000000000100000000110011
#define RVOPC_ZEXT_H_MASK      0b11111111111100000111000001111111

// Zbc (carry-less multiply)
#define RVOPC_CLMUL_BITS       0b00001010000000000001000000110011
#define RVOPC_CLMUL_MASK       0b11111110000000000111000001111111
#define RVOPC_CLMULH_BITS      0b00001010000000000011000000110011
#define RVOPC_CLMULH_MASK      0b11111110000000000111000001111111
#define RVOPC_CLMULR_BITS      0b00001010000000000010000000110011
#define RVOPC_CLMULR_MASK      0b11111110000000000111000001111111

// Zbs (single-bit manipulation)
#define RVOPC_BCLR_BITS        0b01001000000000000001000000110011
#define RVOPC_BCLR_MASK        0b11111110000000000111000001111111
#define RVOPC_BCLRI_BITS       0b01001000000000000001000000010011
#define RVOPC_BCLRI_MASK       0b11111110000000000111000001111111
#define RVOPC_BEXT_BITS        0b01001000000000000101000000110011
#define RVOPC_BEXT_MASK        0b11111110000000000111000001111111
#define RVOPC_BEXTI_BITS       0b01001000000000000101000000010011
#define RVOPC_BEXTI_MASK       0b11111110000000000111000001111111
#define RVOPC_BINV_BITS        0b01101000000000000001000000110011
#define RVOPC_BINV_MASK        0b11111110000000000111000001111111
#define RVOPC_BINVI_BITS       0b01101000000000000001000000010011
#define RVOPC_BINVI_MASK       0b11111110000000000111000001111111
#define RVOPC_BSET_BITS        0b00101000000000000001000000110011
#define RVOPC_BSET_MASK        0b11111110000000000111000001111111
#define RVOPC_BSETI_BITS       0b00101000000000000001000000010011
#define RVOPC_BSETI_MASK       0b11111110000000000111000001111111

// Zbkb (basic bit manipulation for crypto) (minus those in Zbb)
#define RVOPC_PACK_BITS        0b00001000000000000100000000110011
#define RVOPC_PACK_MASK        0b11111110000000000111000001111111
#define RVOPC_PACKH_BITS       0b00001000000000000111000000110011
#define RVOPC_PACKH_MASK       0b11111110000000000111000001111111
#define RVOPC_BREV8_BITS       0b01101000011100000101000000010011
#define RVOPC_BREV8_MASK       0b11111111111100000111000001111111
#define RVOPC_UNZIP_BITS       0b00001000111100000101000000010011
#define RVOPC_UNZIP_MASK       0b11111111111100000111000001111111
#define RVOPC_ZIP_BITS         0b00001000111100000001000000010011
#define RVOPC_ZIP_MASK         0b11111111111100000111000001111111

// Zbkc is a subset of Zbc.

// Zbkx (crossbar permutation)
#define RVOPC_XPERM8_BITS      0b00101000000000000100000000110011
#define RVOPC_XPERM8_MASK      0b11111110000000000111000001111111
#define RVOPC_XPERM4_BITS      0b00101000000000000010000000110011
#define RVOPC_XPERM4_MASK      0b11111110000000000111000001111111

// Zilsd (load/store pair)
#define RVOPC_LD_BITS          0b00000000000000000011000000000011 //  rd[0] == 0
#define RVOPC_LD_MASK          0b00000000000000000111000011111111
#define RVOPC_SD_BITS          0b00000000000000000011000000100011 // rs2[0] == 0
#define RVOPC_SD_MASK          0b00000000000100000111000001111111

// Hazard3 custom instructions

// Xh3b (Hazard3 custom bitmanip): currently just a multi-bit version of bext/bexti from Zbs
#define RVOPC_H3_BEXTM_BITS    0b00000000000000000000000000001011 // custom-0 funct3=0
#define RVOPC_H3_BEXTM_MASK    0b11100010000000000111000001111111
#define RVOPC_H3_BEXTMI_BITS   0b00000000000000000100000000001011 // custom-0 funct3=4
#define RVOPC_H3_BEXTMI_MASK   0b11100010000000000111000001111111

// C Extension
#define RVOPC_ILLEGAL16_BITS   0b0000000000000000
#define RVOPC_ILLEGAL16_MASK   0b1111111111111111
#define RVOPC_C_ADDI4SPN_BITS  0b0000000000000000 // *** illegal if imm 0
#define RVOPC_C_ADDI4SPN_MASK  0b1110000000000011
#define RVOPC_C_LW_BITS        0b0100000000000000
#define RVOPC_C_LW_MASK        0b1110000000000011
#define RVOPC_C_SW_BITS        0b1100000000000000
#define RVOPC_C_SW_MASK        0b1110000000000011

#define RVOPC_C_ADDI_BITS      0b0000000000000001
#define RVOPC_C_ADDI_MASK      0b1110000000000011
#define RVOPC_C_JAL_BITS       0b0010000000000001
#define RVOPC_C_JAL_MASK       0b1110000000000011
#define RVOPC_C_J_BITS         0b1010000000000001
#define RVOPC_C_J_MASK         0b1110000000000011
#define RVOPC_C_LI_BITS        0b0100000000000001
#define RVOPC_C_LI_MASK        0b1110000000000011
// addi16sp when rd=2:
#define RVOPC_C_LUI_BITS       0b0110000000000001 // *** reserved if imm 0 (for both LUI and ADDI16SP)
#define RVOPC_C_LUI_MASK       0b1110000000000011
#define RVOPC_C_SRLI_BITS      0b1000000000000001 // On RV32 imm[5] (instr[12]) must be 0, else reserved NSE.
#define RVOPC_C_SRLI_MASK      0b1111110000000011
#define RVOPC_C_SRAI_BITS      0b1000010000000001 // On RV32 imm[5] (instr[12]) must be 0, else reserved NSE.
#define RVOPC_C_SRAI_MASK      0b1111110000000011
#define RVOPC_C_ANDI_BITS      0b1000100000000001
#define RVOPC_C_ANDI_MASK      0b1110110000000011
#define RVOPC_C_SUB_BITS       0b1000110000000001
#define RVOPC_C_SUB_MASK       0b1111110001100011
#define RVOPC_C_XOR_BITS       0b1000110000100001
#define RVOPC_C_XOR_MASK       0b1111110001100011
#define RVOPC_C_OR_BITS        0b1000110001000001
#define RVOPC_C_OR_MASK        0b1111110001100011
#define RVOPC_C_AND_BITS       0b1000110001100001
#define RVOPC_C_AND_MASK       0b1111110001100011
#define RVOPC_C_BEQZ_BITS      0b1100000000000001
#define RVOPC_C_BEQZ_MASK      0b1110000000000011
#define RVOPC_C_BNEZ_BITS      0b1110000000000001
#define RVOPC_C_BNEZ_MASK      0b1110000000000011

#define RVOPC_C_SLLI_BITS      0b0000000000000010 // On RV32 imm[5] (instr[12]) must be 0, else reserved NSE.
#define RVOPC_C_SLLI_MASK      0b1111000000000011
// jr if !rs2:
#define RVOPC_C_MV_BITS        0b1000000000000010 // *** reserved if JR and !rs1 (instr[11:7])
#define RVOPC_C_MV_MASK        0b1111000000000011
// jalr if !rs2:
#define RVOPC_C_ADD_BITS       0b1001000000000010 // *** EBREAK if !instr[11:2]
#define RVOPC_C_ADD_MASK       0b1111000000000011
#define RVOPC_C_LWSP_BITS      0b0100000000000010
#define RVOPC_C_LWSP_MASK      0b1110000000000011
#define RVOPC_C_SWSP_BITS      0b1100000000000010
#define RVOPC_C_SWSP_MASK      0b1110000000000011

// Zcb simple additional compressed instructions
#define RVOPC_C_LBU_BITS       0b1000000000000000
#define RVOPC_C_LBU_MASK       0b1111110000000011
#define RVOPC_C_LHU_BITS       0b1000010000000000
#define RVOPC_C_LHU_MASK       0b1111110001000011
#define RVOPC_C_LH_BITS        0b1000010001000000
#define RVOPC_C_LH_MASK        0b1111110001000011
#define RVOPC_C_SB_BITS        0b1000100000000000
#define RVOPC_C_SB_MASK        0b1111110000000011
#define RVOPC_C_SH_BITS        0b1000110000000000
#define RVOPC_C_SH_MASK        0b1111110001000011
#define RVOPC_C_ZEXT_B_BITS    0b1001110001100001
#define RVOPC_C_ZEXT_B_MASK    0b1111110001111111
#define RVOPC_C_SEXT_B_BITS    0b1001110001100101
#define RVOPC_C_SEXT_B_MASK    0b1111110001111111
#define RVOPC_C_ZEXT_H_BITS    0b1001110001101001
#define RVOPC_C_ZEXT_H_MASK    0b1111110001111111
#define RVOPC_C_SEXT_H_BITS    0b1001110001101101
#define RVOPC_C_SEXT_H_MASK    0b1111110001111111
#define RVOPC_C_NOT_BITS       0b1001110001110101
#define RVOPC_C_NOT_MASK       0b1111110001111111
#define RVOPC_C_MUL_BITS       0b1001110001000001
#define RVOPC_C_MUL_MASK       0b1111110001100011

// Zclsd load/store pair instructions
#define RVOPC_C_LD_BITS        0b0110000000000000 //  rd[0] == 0
#define RVOPC_C_LD_MASK        0b1110000000000111
#define RVOPC_C_LDSP_BITS      0b0110000000000010 //  rd[0] == 0
#define RVOPC_C_LDSP_MASK      0b1110000010000011
#define RVOPC_C_SD_BITS        0b1110000000000000 // rs2[0] == 0
#define RVOPC_C_SD_MASK        0b1110000000000111
#define RVOPC_C_SDSP_BITS      0b1110000000000010 // rs2[0] == 0
#define RVOPC_C_SDSP_MASK      0b1110000000000111

// Zcmp push/pop instructions
#define RVOPC_CM_PUSH_BITS     0b1011100000000010
#define RVOPC_CM_PUSH_MASK     0b1111111100000011
#define RVOPC_CM_POP_BITS      0b1011101000000010
#define RVOPC_CM_POP_MASK      0b1111111100000011
#define RVOPC_CM_POPRETZ_BITS  0b1011110000000010
#define RVOPC_CM_POPRETZ_MASK  0b1111111100000011
#define RVOPC_CM_POPRET_BITS   0b1011111000000010
#define RVOPC_CM_POPRET_MASK   0b1111111100000011
#define RVOPC_CM_MVSA01_BITS   0b1010110000100010
#define RVOPC_CM_MVSA01_MASK   0b1111110001100011
#define RVOPC_CM_MVA01S_BITS   0b1010110001100010
#define RVOPC_CM_MVA01S_MASK   0b1111110001100011

#define _RVOPC_MATCH(x, instr_mask, instr_bits) (((x) & (instr_mask)) == (instr_bits))
#define RVOPC_MATCH(x, instr) _RVOPC_MATCH(x, RVOPC_ ## instr ## _MASK, RVOPC_ ## instr ## _BITS)

static const char *friendly_reg_names[32] = {
	"x0", "ra", "sp", "gp", "tp", "t0", "t1", "t2", "s0", "s1", "a0", "a1", "a2",
	"a3", "a4", "a5", "a6", "a7", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9",
	"s10", "s11", "t3", "t4", "t5", "t6"
};

#endif
